1. Technical Field
This invention relates generally to an apparatus, method and medium for increasing the throughput of a semiconductor wafer processing facility. More particularly, the invention provides various efficiency enhancements for such a facility, including a multi-slot cool down chamber, the use of multiple wafer priority levels to control wafer movement, and a look-ahead scheduling process.
2. Related Information
Automated semiconductor fabrication facilities which employ a single-wafer, multi-chamber design are well known. As one example, the Centura model 5200 sold by Applied Materials, Inc. of Santa Clara, Calif. (see FIG. 1) provides a plurality of chambers arranged around a central processing station which includes a robot arm 101 for moving a silicon wafer 102 between the chambers. Each wafer is stepped through a series of processes (typically one per chamber) which results in the formation of various layers on the wafer which are later used to form a semiconductor device.
As shown in FIG. 1, two load lock chambers 109 and 110 may each include a cassette which forms a plurality of slots (109a and 110a, respectively) for holding a number of wafers. As one example, each cassette may hold 25 wafers. A plurality of processing chambers 104 through 107 each include equipment which performs a processing step on a wafer inserted into the chamber through a corresponding slot (104a through 107a). For example, one process chamber may perform a chemical vapor deposition (CVD) process on a wafer, while another chamber may perform an etching process. A process controller 111, which may comprise a digital computer (such as an embedded Motorola 68040 CPU with a realtime operating system) including sequencing software, may be used to control the timing and movement of wafers through the various chambers to effect the desired process steps on each wafer.
In addition to the process chambers, an orientation chamber 103 may be included to orient each wafer prior to processing. This generally entails finding the center of a wafer inserted into the chamber and passing this center point information to process controller 111 so that robot arm 101 can properly orient the wafer prior to insertion into one of the process chambers. Additionally, a cool down chamber 108 is generally used to allow wafers to cool down between processing steps or after processing is completed.
In general, process controller 111 causes robot arm 101 to remove wafers from a load lock chamber 110, orient the wafer in chamber 103, move the wafer through one or more of the process chambers 104 through 107 according to a timed xe2x80x9crecipexe2x80x9d for the wafer, cool down the wafer in cool down chamber 108, and place the processed wafer into a load lock chamber 109. Depending on the particular xe2x80x9crecipexe2x80x9d, a wafer may be moved from load lock 110 to process C (chamber 107), then to process A (chamber 106), then cooled down (chamber 108), then moved back to process C again (chamber 107), cooled down again (chamber 108), then moved to load lock 109. Of course, more than one wafer may be processed simultaneously if the steps are properly synchronized.
Each wafer which is dispensed from load lock 110 may be stepped through the same process steps to produce the same type of wafer. Alternatively, different wafers from the same load lock may be programmed to undergo a different xe2x80x9crecipexe2x80x9d involving different steps and/or process times, such that different types of wafers are produced.
A bottleneck has been found to occur in the conventional wafer processing method described above when multiple wafers are simultaneously processed in an overlapping sequence. This bottleneck has been found to occur at the cool-down chamber 108. This cool-down chamber is needed primarily to prevent damage to load lock chamber 109 after heating a wafer in one of the processing chambers 104 through 107, and also to cool down wafers between certain processing steps. However, the wafer processing steps are relatively short compared with the time required in cool down chamber 108, thus causing the cool down chamber to limit the throughput of the entire apparatus. The fact that the conventional cool down chamber only has a single slot for holding a wafer also contributes to this bottleneck.
In addition to the bottleneck caused by the cool down chamber, conventional wafer scheduling techniques generally contemplate moving wafers sequentially based on their wafer identification number (i.e., the first wafer to be removed from load lock 110 will be deemed wafer #1, the second one will be deemed wafer #2, etc.) rather than on the status of the wafer process itself. The present inventors have found that this scheduling paradigm also results in a loss of efficiency.
For example, if wafer #1 is in process B (chamber 105) and is ready to be moved to cool down chamber 108, while at the same time wafer #2 is in load lock 110 and ready to be moved into process D (chamber 104), the conventional scheduler will first move wafer #1 to the cool down chamber. However, for reasons which will become evident shortly, this may not be as efficient as first moving wafer #2 into process D (chamber 104) prior to moving wafer #1 to the cool down chamber. Thus, potential efficiency is lost.
The above-described inefficiency is presented by way of simplified illustration in FIG. 2. In FIG. 2, time periods are indicated on the horizontal axis and each potential processing step is shown on the vertical axis. Each numbered circle represents a single wafer, and arrows between circles represent wafer movement between chambers by way of a robot arm.
Suppose, for example, that a first wafer (wafer #1) is to be subjected to process A for one time period, process B for three time periods, then a cool down period before being moved out of the processing sequence. The aforementioned sequence constitutes the xe2x80x9crecipexe2x80x9d for this wafer.
Assume that a second wafer (wafer #2) is to be subjected to process A for three time periods, process C for four time periods, then a cool down period. Other wafers #3 and #4, after being removed from a load lock cassette, will be subjected to similar processing sequences.
As can be seen at time period 0 in FIG. 2, the robot arm first moves wafer #1 into the chamber which performs process A (step 200). Next, after a single time period, the robot arm moves wafer #1 from process A to process B (step 201). Thereafter, wafer #2 is removed from the load lock area and moved into process A (step 202) where it remains for three time periods.
At time period 4, wafer #1 is ready to be moved to the cool down chamber, which occurs in step 204. Thereafter, in step 205, wafer #2 is moved to process C, where it remains for four time periods. Then, at time period 7, wafer #1 is ready to be moved out of the cool down chamber, and this step occurs as indicated at 207. However, it would have been more efficient at time period 7 to bring another new wafer into one of the processing chambers prior to removing cooled wafer #1 (i.e., there is no inefficiency in delaying the removal of a cooled wafer). As can be seen in step 208, wafer #3 is not brought into process A until time period 8 because of the movement of cooled wafer #1 in step 207. This inefficiency causes a decrease in wafer throughput.
Continuing with the scenario of FIG. 2, at step 209 wafer #2 is moved from process C to the cool down chamber. However, at the same time, wafer #4 could have been brought into process B, since that chamber was available and ready for use. Thus, step 210 (movement of wafer #4 into process B) was unnecessarily delayed for at least one time period. This sequence (moving a processed wafer before an unprocessed or xe2x80x9cvirginxe2x80x9d wafer) illustrates another inefficiency of conventional wafer processes.
Various manifestations of the aforementioned problem are illustrated more generally in FIG. 3, which is not intended to mirror the example shown in FIG. 2. In FIG. 3, wafer group 301 represents the order in which each wafer has (or will) complete its processing and is ready to be moved to its next chamber. Thus, for example, wafer #2 is the first wafer which will have completed its process step, which occurs prior to the process subjected to wafer #1. In other words, this sequence represents the order in which wafers will become idle (and thus waste time) if not moved.
However, as shown in movement queue 302, conventional wafer sequencing processes typically wait until wafer #1 is ready to move before moving wafer #2. One reason for doing this is to ensure, for example, that deadlock situations do not occur which might disrupt the wafer processing sequence. In other words, blindly moving wafers based on their order of process step completion (order 301) could result in havoc because situations may arise where all chambers are full and none will become available because the sequencer will forever wait for an empty chamber. Even leaving one chamber empty will not solve this problem, particularly for sequences which require different recipes for different wafers. Moreover, certain wafer recipes require that a wafer xe2x80x9crevisitxe2x80x9d a chamber for further processing after completing another process step. The simple wafer movement ordering shown in 302 thus avoids these problems.
The conventional approach of moving wafers on the basis of wafer identification numbers also ensures that the earliest wafers in are the earliest wafers out. While this straightforward scheme avoids many problems, it also results in inefficiencies for the reasons outlined above.
Yet another inefficiency inherent in conventional wafer scheduling techniques concerns delaying a soon-to-be-scheduled wafer movement because of latency in the robot arm movement. For example, the wafer movement mechanism 101 may require, e.g., 8 seconds to move a wafer from one chamber to another chamber. If a relatively low priority wafer movement begins (e.g., moving a cooled wafer) which occupies the mechanism for 8 seconds, other more important wafer transfers which are scheduled to begin in less than 8 seconds (e.g., moving a wafer between two processes) may be delayed. Thus, efficiency is again compromised.
Finally, load locks 109 and 110 may comprise an elevator mechanism which moves the cassettes up or down to be aligned with robot arm 101. Conventional techniques for moving wafers between load locks and other chambers generally involve sequentially commanding the robot arm to move to the load lock, followed by a command to raise or lower the elevator to move the load lock into proper alignment position. This sequential positioning arrangement wastes time because the elevator movement mechanism, like the wafer movement mechanism, involves a latency on the order of seconds which is added to the robot arm movement time.
Thus, conventional wafer scheduling techniques leave much room for efficiency improvement.
The present invention increases the efficiency of conventional single-wafer processor scheduling systems. In various embodiments, the present invention contemplates providing a multi-slot cool down chamber which allows more than one wafer to be simultaneously cooled down in a stacked configuration. Additionally, a wafer prioritization scheme classifies wafers based on their processing completion stage, and schedules their sequential movement based on their priority. A sequencer look-ahead feature overcomes problems caused by robot arm movement initiations which occur shortly prior to process expiration times for other wafers. Finally, an elevator movement command can be initiated prior to movement of the robot arm to minimize the amount of time required to align the robot arm with a slot in a wafer storage slot. Other features and advantages will become apparent through the following detailed description, the figures, and the appended claims.